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Discoveries Requiring Inspiration and Perspiration One of the valid concerns related to future technology development is the possibility that Moore s Law may be dissipated in the near future The technical and physical obstacles that loom ahead are of concern How complex can chips become is an open question One problem is power leakage as chips become more power hungry Chips with billions of transistor can leak up to 70 watts of power, causing cooling problems In addition, it is possible that circuit dimensions cannot get much smaller than the current 65 nanometers without increasing production dif culties In 2004, we were mass producing the 90-nm IC By 2006, migration to 65 nm began Changing from 90-nm to 65-nm design rules was quick because it required no changes in the fabrication process Back in 1988, IBM fabricated the world s smallest transistor at that time using 70-nm design rules.

It ran on a power supply of only 1 volt rather than the usual 5 volts, but required nitrogen cooling Today these eld effect transistors (FETs) run at room temperature In late 2003, NEC built a FET with a 5-nm gate length and IBM built one with a 6-nm gate length These are 10 times smaller than what s used in production now So we already know that transistors will work at scales that are an order of magnitude smaller than today s technology Instead of focusing on acquiring more speed from a single processor, which could be a dead end, innovators are also developing multicore processors: microprocessors using four to eight parallel cores By working in parallel, the total throughput of the processor is greatly increased Dual and quad cores are already being produced commercially Parallel advances in hardware will optimize the threaded software of network services.

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induced by the ionosphere is known to be inversely proportional to the square of frequency, ionospheric range error can be estimated accurately by comparing the times of arrival of the L1 and L2 signals. Details on the calculations appear in 5. 2. Facilitates carrier phase ambiguity resolution. In high-accuracy GPS differential positioning, the range estimates using carrier phase measurements are precise but highly ambiguous due to the periodic structure of the carrier. The ambiguity is more easily resolved (by various methods) as the carrier frequency decreases. By using L1 and L2 carrier frequencies, the ambiguity resolution can be based on their frequency difference (1575:42 1227:6 MHz), which is smaller than either carrier frequency alone, and hence will result in better ambiguity resolution performance. 3. Provides system redundancy (primarily for the military user).

Discoveries Requiring New Proof of Principle What about extending Moore s Law If we reach a physical limit to Moore s Law, we will require new discoveries in breakthrough phenomena demonstrating new proofs of principle The following are some of the leading candidates 3D Molecular Chips One alternative is building 3D chips, in which layers of transistors form a high rise12 New technologies that could lead to molecular three-dimensional computing include nanotubes, nanotube molecular computing, and self-assembly in nanotube circuits Matrix Semiconductor, Inc is already building three-dimensional circuits using conventional silicon lithography13 They are manufacturing memory chips with vertically stacked planes..

The benefits resulting from WWW-TeleBel are mainly in the area of customer relations. It is cheaper to hold on to a customer than it is to bring in a new one. In addition, WWW-TeleBel provides extra customer information. This may help increase turnover. Benefits have been summarized in Exhibit 5.8. The net present value of the benefits amounts to $847,000.

So the variance is var[x] = E[x2] x2 = 25.5 (4.5)2 = 25.5 20.25 = 4.25 Note that the variance we obtained from the 12-toss example (see equation A.6) is slightly different (4.992). The standard deviation for our uniformly distributed variable is:

Given that there are different locking modes, the definition of a concurrencycontrol scheme always includes the definition of compatibility between locks. Figure 11.4 shows the lock compatibility matrix for a concurrency control scheme that includes only read and write locks. This is the minimal lock compatibility matrix. More complicated ones are used in practice. The scheme defines that a read lock is compatible with another read lock, but incompatible with a write lock. Furthermore, write locks are incompatible with each other. Read Read Write _ Write _ _

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